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RC96V24DP
Single Device Data/Fax Modem Data Pump
The Rockwell RC96V24DP is a low power, V.22 bis 2400 bps data/fax modem data pump in a single VLSI package. The RC2324DPL is identical to the RC96V24DP except fax modes are not provided. In this document, all references to the RC96V24DP also apply to the RC2324DPL except for the fax modes and as otherwise noted. The modem operates over the public switched telephone network (PSTN), as well as on point-to-point leased lines. The modem supports data modes meeting the requirements specified in CCITT recommendations V.22 bis, V.22, V.23, and V.21, as well as Bell 212A and Bell 103. The modem supports fax modes meeting the requirements specified in CCITT V.29, V.27 ter, and V.21 channel 2 synchronous. Internal HDLC support eliminates the need for an external serial input/output (SIO) device or comparable functions in the host controller in products incorporating error correction and T.30 protocols. The modem includes two CMOS VLSI functions - a digital signal processor (DSP) and an integrated analog function (IA). The RC96V24DP integrates these functions into a single 68-pin plastic leaded chip carrier (PLCC). Detailed hardware and software interface information is described in the Designer's Guide (Order No. 822).
Product Features
* * Single CMOS VLSI device Low power requirements - Single voltage: + 5 Vdc 5% - Operating: 300 mW (typical) - Sleep: 15 mW (typical) 2-wire operation - Full- duplex (FDX) for data modes - Half-duplex (HDX) for fax modes Data configurations: - V.22 bis, V.22, V.23, V.21 - Bell 212A, Bell 103 Fax configurations (RC96V24DP): - V.29, V.27 ter, V.21 Channel 2 Voice mode DTMF detection Receive dynamic range: -9 dBm to -43 dBm Transmit level: -10 dBm 1 dB using internal hybrid circuit; attentuation selectable in 1 dB steps Multi-mode data/fax detection support V.22 bis fallback/fall-forward -2400/1200 bps Serial data: synchronous and asynchronous Parallel data: synchronous (including HDLC) and asynchronous Programmable ring detect Programmable dialer Programmable tone detect bandpass filters Adjustable speaker output to monitor received signal Diagnostics Host bus interface memory for configuration, control, and parallel data; 8086 microprocessor bus compatible 5-pin serial data interface; TTL compatible Equalization - Adaptive equalizer in receiver - Selectable and programmable fixed compromise equalizers in both receiver and transmitter Loopback configurations - Local analog, local digital, and remote digital Answer and originate handshake in data modes Training sequences for fax modes Leased line operation
*
*
* * * * *
Functional Block Diagram
2
* * * * * * * *
TELEPHONE LINE INTERFACE
SERIAL INTERFACE (5)
2
* *
RC96V24DP MODEM DEVICE SPEAKER AMPLIFIER (OPTIONAL)
* *
HOST PARALLEL BUS INTERFACE (17)
*
4 EYE PATTERN GENERATOR (OPTIONAL)
* * *
D96V24DSA
Ordering Information
Marketing Number
RC96V24DP RC96V24DP RC9624DP RC9624DP RC2324DPL RC2324DPL
Manufacturing Number
R6653-12 R6653-17 R6653-16 R6653-21 R6653-15 R6653-20
Package
68 pin PLCC 100 pin PQFP 68 pin PLCC 100 pin PQFP 68 pin PLCC 100 pin PQFP
NOTE: RC2324DPL does not support fax capabilities. RC9624DP does not support voice.
Copyright (c) 1998 Rockwell Semiconductor Systems, Inc. All rights reserved. Print date: September 1998 Rockwell Semiconductor Systems, Inc. reserves the right to make changes to its products or specifications to improve performance, reliability, or manufacturability. Information furnished is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by its implication or otherwise under any patent or intellectual property rights of Rockwell Semiconductor Systems, Inc. Rockwell Semiconductor Systems, Inc. products are not designed or intended for use in life support appliances, devices, or systems where malfunction of a Rockwell Semiconductor Systems, Inc. product can reasonably be expected to result in personal injury or death. Rockwell Semiconductor Systems, Inc. customers using or selling Rockwell Semiconductor Systems, Inc. products for use in such applications do so at their own risk and agree to fully indemnify Rockwell Semiconductor Systems, Inc. for any damages resulting from such improper use or sale. Specifications are subject to change without notice.
PRINTED IN THE UNITED STATES OF AMERICA
1.0 Functional Description
1.1 Overview
The Rockwell RC96V24DP is a low power, V bis 2400 bps data/fax modem .22 data pump in a single VLSI package.
1.2 Technical Specifications
1.2.1 Configurations And Rates
The selectable modem configurations, along with the corresponding signaling (baud) rates and data rates, are listed in Table 1-1 (CONF bits). Note: Bit names refer to control or status bits in DSP interface memory which are set or reset by the host processor (see Table 3-1 and Table 3-2).
1.2.2 Data Encoding
The data encoding conforms to CCITT recommendations V .29, V ter, V bis, .27 .22 V .22, V .23, or V .21, or to Bell 212A or 103, depending on the selected configuration.
1.2.3 Tone Generation
Answer Tone: A CCITT (2100 15 Hz) or Bell (2225 10 Hz) answer tone can be generated. Guard Tone: A1800 20 Hz guard tone can be generated (enabled by the GTE bit). DTMF Tones: Dual tone multi-frequency (DTMF) tones can be generated with a frequency accuracy of 1.5%. User Defined Tones: A user-defined single or dual tone can be generated from 200 Hz to 3000 Hz 5 Hz.
D96V24DSA
1-1
1.0 Functional Description
1.2 Technical Specifications
RC96V24DP
Single Device Data/Modem Data Pump
1.2.4 Tone Detection
Answer Tone and Call Progress Tones: Tones can be detected as follows: * * * * * * Call progress frequency range: 340 5 Hz to 640 5HZ Answer tone frequency ranges: CCITT (2100 15Hz), Bell (2225 10 Hz), or Bell FSK originate tone (1270 10 Hz) Detection range: -9 dBm to -43 dBm Default detection threshold: -43 dBm Response time: 75 2 ms The passband and tone detect threshold can be changed in DSP RAM.
V.23 and V21 Tones: Tones can be detected as follows: * * * * * * V forward channel mark: 1300 10 Hz .23 V backward channel mark: 390 10 Hz .23 V high band mark (1650 10 Hz) or low band mark (980 10 Hz) .21 Detection range: -9 dBm to -43 dBm Default detection threshold: -43 dBm Response time: 25 2 ms
The passbands and tone detect thresholds can also be changed in the DSP RAM. 1.2.4.1 DTMF Detection 1.2.4.2 Equalizers The modem can detect a valid DTMF tone pair (indicated by DTDET) and load a corresponding hexadecimal code into the modem interface memory (DTDIG). Equalization functions are incorporated that improve performance when operating over low quality lines. Automatic Adaptive Equalizer. An automatic adaptive equalizer in the receiver compensates for transmission line amplitude and group delay distortion. Updating of the taps can be enabled or disabled (EQFZ bit). The equalizer taps can also be reset (EQRES bit). Fixed Compromise Equalizers. Fixed compromise equalizers are provided in the transmitter and receiver. The equalizers are programmable in DSP RAM. 1.2.4.3 Transmit Level 1.2.4.4 Transmit Timing The transmitter output level is -10 dBm 1 dB using the internal hybrid circuit. The attentuation is selectable from 0 dBm to -15 dBm in 1 dB steps (TLVL bits). Transmitter timing is selectable between internal (0.01%), external, or loopback (TXCLK bits). When external clock is selected, the external clock rate must equal the desired data rate 0.01% with a duty cycle of 50 20%. The modem incorporates a self-synchronizing scrambler/descrambler satisfying the applicable CCITT or Bell requirement. The scrambler and descrambler can be enabled or disabled (SDIS and DDIS bits, respectively).
1.2.4.5 Scrambler/ Descrambler
1-2
D96V24DSA
RC96V24DP
Single Device Data/Modem Data Pump
1.0 Functional Description
1.2 Technical Specifications
1.2.4.6 Receive Level
The receiver satisfies performance requirements for a received line signal from -9 dBm to -43 dBm. The default RLSD turn-on and RLSD turn-off thresholds are -43 dBm and -48 dBm, respectively. The RLSD threshold levels are programmable in DSP RAM. The modem can track a frequency error up to 0.03% in the associated transmit timing source. The modem can track a frequency offset up to 7 Hz in the received carrier with less than a 0.2 dB degradation in bit error rate (BER).
1.2.4.7 Receiver Timing 1.2.4.8 Carrier Recovery
D96V24DSA
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1.0 Functional Description
1.2 Technical Specifications
RC96V24DP
Single Device Data/Modem Data Pump
Table 1-1. Configurations, Signaling and Data Rates
Transmitter Carrier Frequency (Hz) 0.01% Data Rate (bps) Baud (Symbols/ Sec) Bits Per Constellation Sample Rate (Samples/ Sec)
Configuration Data Modes V.22 bis V.22
Modulation
Answer2
Originate2
0.01%
Symbol
Points
QAM DPSK
2400 2400 2400 2400 2225 M 2025 S 1650 M 1850 S 1300 M 2100 S 390 M 450 S
1200 1200 1200 1200 1270 M 1070 S 980 M 1180 S 1300 M 2100 S 390 M 450 S
24003 12003 6003 12003 0-3004 0-3004 1200
600 600 600 600 0-3004 0-3004 1200
4 2 1 2 1 1 1
16 4 2 4 1 1 1
7200 7200 7200 7200 7200 7500 96005 7200
Bell 212A Bell 103 V.21 V.23 Forward Channel
5
DPSK FSK FSK FSK
V.23 Backward Channel5 Fax Modes6 V.29
FSK
75
75
1
1
QAM QAM QAM DPSK DPSK FSK
1700 1700 1700 1800 1800 1650 M 1850 S
1700 1700 1700 1800 1800 1650 M 1850 S
9600 7200 4800 4800 2400 300
2400 2400 2400 1600 1200 300 600 600
4 3 2 3 2 1
16 8 4 8 4 1
9600 7200 9600 9600 9600 9600 7200 7200
V.27 ter V.21 channel 2 Dial/Call Progress Mode Tone Generator/ Tone Detector Mode
Notes: (1) Modulation legend:
QAM Quadrature Amplitude Modulation DPSK Differential Phase Shift Keying FSK Frequency Shift Keying (2) M indicates a mark condition; S indicates a space condition. (3) Synchronous accuracy = 0.01%; asynchronous accuracy = -2.5% to +1.0% (+2.3% if extended overspeed is selected). (4) Value is upper limit for serial (e.g. 0-300). (5) RC2324DPL only. (6) RC96V24DP only. (7) 9600 samples per sec in V.23 FDX Tx75/Rx1200; 7200 samples per second in V.23 FDX Tx1200/Rx75.
1-4
D96V24DSA
RC96V24DP
Single Device Data/Modem Data Pump
1.0 Functional Description
1.2 Technical Specifications
Table 1-2. Dial Digits/Tone Pairs Dial Digit
1
Tone 1 (Hz)
697
Tone 2 (Hz)
1209
2
697
1336
3
697
1447
4 5 6 7 8 9 0 * # Spare B
770 770 770 852 852 852 941 941 941 967
1209 1336 1447 1209 1336 1477 1336 1209 1477 1633
1.2.4.9 RTS-CTS TurnOn and Turn-Off Sequences
RTS ON to CTS ON and RTS OFF to CTS OFF response times are listed in Table 1-3. In V .21, the transmitter turns off within 10 ms after RTS goes OFF. For V .29, the turn-off sequence consists of approximately 5 ms of remaining data and scrambled ones followed by a 50 ms period of no transmitted energy. For V ter, the turn-off sequence consists of approximately 7 ms of .27 remaining data and scrambled ones at 1200 baud or approximately 7.5 ms of data and scrambled ones at 1600 baud followed by a 20 ms period of no transmitted energy.
1.2.5 Serial or Parallel Interface
The TPDM bit selects serial or parallel interface. Serial Interface. The five hardware lines (RXD, TXD, TDCLK, RDCLK, and XTCLK) are supported by four control and status bits in the interface memory (CTS, DSR, RTS, and RLSD). Parallel Interface. A 8086-compatible parallel microprocessor bus is supported.
D96V24DSA
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1.0 Functional Description
1.2 Technical Specifications
RC96V24DP
Single Device Data/Modem Data Pump
1.2.6 Voice Mode
Transmit Voice. Transmit voice samples can be sent to the modem digital-toanalog converter (DAC) from the host through the transmit data buffer. Receive Voice. Received voice samples from the modem analog-to-digital converter (ADC) can be read by the host from the receive data buffer.
1.2.7 Asynchronous Conversion
Asynchronous mode is selected by the ASYNC bit. The asynchronous character format is 1 start bit, 5 to 8 data bits (WDSZ bits), an optional parity bit (PARSL and PEN bits), and 1 or 2 stop bits (STB bit). Valid character size, including all bits, is 7, 8, 9, 10 or 11 bits per character.
Table 1-3. RTS-CTS Response Times Configuration
Data Modes V.22 bis, V.22, and Bell 212A (CC bit = 0) V.22 bis, V.22, and Bell 212A (CC bit =1) V.21 and Bell 103 V.23 (RC96V24DP and RC2324DPL only) Fax Modes (RC96V24DP only) Echo Protector Tone Disabled (NV25 = 1) V.29 (All speeds) V.27 4800 V.27 2400 V.21 Echo Protector Tone Enabled (NV25 = 0) V.29 (All speeds) V.27 4800 V.27 2400 V.21 253 ms 1103 ms 1338 ms 3095 ms 253 ms 898 ms 1133 ms 20 ms
Turn On Time
Turn Off Time
2 ms
270 ms 2-5 ms 11 ms
2 ms 2 ms
10 ms
2 ms
2 ms 2 ms
9 ms 4 ms
2 ms 2 ms
9 ms 4 ms
Signalling Rate Range. Signalling rate range is selectable by the EXOS bit: * Basic range: +1% to -2.5% * Extended overspeed range: +2.3% to -2.5% Break. Break is handled as described in V bis. .22
1-6
D96V24DSA
RC96V24DP
Single Device Data/Modem Data Pump
1.0 Functional Description
1.2 Technical Specifications
1.2.7.1 Power and Environmental Requirements
The power requirements are specified in Table 1-4. The environmental specifications are listed in Table 1-5.
Table 1-4. Modem Power Requirements Voltage
5VDC 5%
Mode
Operating Sleep
Current (Typ) @ 25C
60 mA 3 mA
Current (Max) @ 0C
90 mA 4.5 mA
Note:
Input voltage ripple 0.1 volts peak-to-peak. The amplitude of any frequency between 20 kHz and 150 kHz must be less than 500 microvolts peak.
Table 1-5. Modem Environmental Specifications Parameter
Temperature Operating Storage Relative Humidity 0 C to 70 C (32 F to 158 F) -40 C to 80 C (-40 F to 176 F) Up to 90% noncondensing, or a wet bulb temperature up to 35 C, whichever is less. -200 feet to +10,000 feet
Specification
Altitude
D96V24DSA
1-7
1.0 Functional Description
1.2 Technical Specifications
RC96V24DP
Single Device Data/Modem Data Pump
1-8
D96V24DSA
2.0
2.0 Hardware Interface
The modem functional hardware interface signals are shown in Figure 2-1. In this diagram, any point that is active low is represented by a small circle at the signal point. Edge triggered inputs are denoted by a small triangle (e.g., TDCLK). OpenCollector (open-source or open-drain) outputs are denoted by a small half-circle (e.g., IRQ). Active low signals are overscored (e.g., POR). A dock intended to activate logic on its rising edge (low-to-high transition) is called active low (e.g., RDCLK), while a clock Intended to activate logic on its falling edge (high-to-low transition) is called active high (e.g., TDCLK). When a clock input is associated with a small circle, the input activates on a falling edge. If no circle is shown, the input activates on a rising edge. The modem pin assignments are shown in Figure 2-2. The pin assignments are listed by pin number in Table 2-1. The hardware interface signal functions are summarized by major interface in Table 2-2. The digital and analog interface characteristics are defined in Table 2-3 and Table 2-4, respectively.
D96V24DSA
2-1
2.0 Hardware Interface
RC96V24DP
Single Device Data/Modem Data Pump
Figure 2-1. RC9623DP Functional Interface Signals
OSCILLOSCOPE TXD TDCLK SERIAL INTERFACE XTCLK RXD EYEX RDCLK EYEY EYESYNC EYE PATTERN GENERATOR (OPTIONAL)
READ WRITE DATA BUS (8) HOST PROCESSOR BUS INTERFACE ADDRESS BUS (5)
RC96V24DP MODEM DEVICE
D0-D7 RS0-RS4
EYECLK
RXA TXA1 TXA2
DECODER
CS RADVR IRQ RING RBDVR
TELEPHONE LINE INTERFACE
+5V XTLI CRYSTAL XTLO
SPKR +5V DGND RESET AGND
SPEAKER AMPLIFIER (OPTIONAL)
NOTE: REQUIRED EXTERNAL COMPONENTS ARE NOT SHOWN
2-2
D96V24DSA
RC96V24DP
Single Device Data/Modem Data Pump
2.0 Hardware Interface
Figure 2-2. RC9623DP Pin Signals
EYESYNC EYEX EYEY RING SLEEP TEST1 RS0 RS1 RS2 RS3 RS4 READ CS WRITE IRQ D0 D1 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
RESET XTAI XTALP +5VD GP18 GP16 XTCLK DGND1 TXD TDCLK TRSTO TSTBO TDACO RADCI RAGCO MODEO RSTBO
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
D2 D3 D4 D5 D6 D7 DGND2 SPKR +5VA MODEI TSTBI TRSTI TDACI RADCO RRSTI RSTBI NC
Table 2-1. RC9623DP Modem Device Pin Signals Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14
RRSTO RDCLK RXD TXA2 TXA1 RXA RFILO AGCIN VC NC NC NC RBDVR AGND RADVR SLEEPI RADCI
Signal Name
RS2 RS1 RS0 TEST1 SLEEP RING EYEY EYEX EYESYNC RESET XTLI XTLO +5VD GP18
I/O Type
IA IA IA
OA
OB OB OB ID IE OB
OA
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2.0 Hardware Interface
RC96V24DP
Single Device Data/Modem Data Pump
Table 2-1. RC9623DP Modem Device Pin Signals (Continued) Pin Number
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
Signal Name
GP16 XTCLK DGND1 TXD TDCLK TRSTO TSTBO TDACO RADCI RAGCO MODEO RSTBO RRSTO RDCLK RXD TXA2 TXA1 RXA RFILO AGCIN VC NC NC NC RBDVR AGND RADRV SLEEP1 RAGCI NC RSTBI
I/O Type
OA IA
IA OA MI MI MI MI MI MI MI MI OA OA O(DD) O(DD) I(DA) MI MI
OD
OD IA MI
MI
2-4
D96V24DSA
RC96V24DP
Single Device Data/Modem Data Pump
Table 2-1. RC9623DP Modem Device Pin Signals (Continued) Pin Number
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
2.0 Hardware Interface
Signal Name
RRSTI RADCO TDACI TRSTI TSTBI MODE1 +5VA SPKR DGND2 D7 D6 D5 D4 D3 D2 D1 D0 IRQ WRITE CS READ RS4 RS3
I/O Type
MI MI MI MI MI MI
O(OF)
IA/OB IA/OB IA/OB IA/OB IA/OB IA/OB IA/OB IA/OB OC IA IA IA IA IA
Notes: (1) MI = Modem Interconnection (2) NC = No connection (may have internal connection; leave pin disconnected (open). (3) I/O types are described in Table 2-3 (digital signals) and Table 2-4 (analog signals).
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2.0 Hardware Interface
RC96V24DP
Single Device Data/Modem Data Pump
Table 2-2. Hardware Interface Signal Definitions Label I/O Type
OVERHEAD SIGNALS XTLI IEOB Crystal/Clock ln and Crystal Out. The DSP must be connected to an external crystal circuit consisting of a 24.00014 MHz crystal and two capacitors. Alternatively, XTLI, may be driven with a buffered clock (e.g., square wave generator) or a sine wave oscillator. Reset. The active low RESET input resets the internal modem logic. Upon transition of RESET from low-to-high, the DSP interface memory bits are set to the default values. +5V Digital Supply. +5V 5% is required. +5V Analog Supply. +5V 5% is required. Digital Ground. Analog Ground. SERIAL INTERFACE Five TTL-level hardware interface circuits implement a CCITT V.24-compatible serial data interface with control signals provided through the DSP interface memory. RDCLK OA Receive Data Clock. In synchronous mode, the modem outputs a Receive Data Clock (RDCLK in the form of 50 1% duty cycle square wave. The low-to-high transitions of this output coincide with the center of received data bits. Transmit Data Clock. In synchronous mode, the modem outputs a Transmit Data Clock (TDCLK). The TDCLK clock frequency is data rate 0.01% with a duty cycle of 50 1%. External Transmit Clock. In synchronous mode, an external transmit data clock input (XTCLK) can be supplied. Received Data. The modem presents received serial data on the Received Data (RXD) output and to the interface memory Receive Data Register (RBUFFER) in both serial and parallel modes. Transmitted Data. The modem obtains serial data to be transmitted on the TXD input in serial mode, or from the interface memory Transmit Data Register (TBUFFER) in parallel mode. (See TPDM bit.) PARALLEL MICROPROCESSOR INTERFACE Address, data, control and interrupt hardware interface signals implement an 8086compatible parallel microprocessor interface to a host processor. This parallel interface allows the host to change modem configuration, read or write channel and diagnostic data, and supervise modem operation by writing control bits and reading status bits. D0-D7 CS IA/OA IA Data Lines. Eight bidirectional data lines (DO-D7) provide parallel transfer of data between the host and the modem. Chip Select. The active low Chip Select (CS) input enables parallel data transfer over the microprocessor bus.
Signal/Definition
RESET +5VD +5VA DGND DGND
ID PWR PWR GND GND
TDCLK XTCLK
OA IA
RXD TXD
OA IA
2-6
D96V24DSA
RC96V24DP
Single Device Data/Modem Data Pump
Table 2-2. Hardware Interface Signal Definitions (Continued) Label I/O Type Signal/Definition
PARALLEL MICROPROCESSOR INTERFACE (con't) RS0-RS4 IA
2.0 Hardware Interface
Register Select Lines. The five active high Register Select inputs (RS0 - RS4) address Interface memory registers in the modem when CS is low. These lines are typically connected to address lines A0-A4 to address one of 32 8-bit internal interface memory registers (00-1F). The selected register can be read from, or written into, via the 8-bit parallel data bus (DO-D7). Read Enable and Write Enable. Reading or writing is controlled by the host pulsing either READ or WRITE input low, respectively, during the microprocessor bus access cycle. During a write cycle, data from the data bus is copied into the addressed DSP interlace memory register, with high and low bus levels representing one and zero bit states, respectively.
READ WRITE
IAIA
IRQ
OA
Interrupt Request. The IRQ output structure is an open-drain field-effect-transistor (FET). The IRQ output can be enabled in the interface memory to allow immediate indication of change of conditions in the modem. The use of IRQ is optional depending upon modem application. HYBRID CIRCUIT
TXA1 TXA2 RXA VC
O(DF)
Transmit Analog 1 and 2. The TXA1 and TXA2 outputs are differential outputs 180 degrees out of phase with each other. Receive Analog. RXA is a single-ended receive data input from the telephone line interface or an optional external hybrid circuit. Centerpolnt Voltage. VC is a +2.5 VDC centerpoint voltage which serves as the internal 'analog ground' reference point.
I(DA) OA
TELEPHONE LINE INTERFACE RADVR OD Relay A Driver. RADVR is an open drain output which can directly drive a relay with greater than 360 Q coil resistance and having a 'must operate' voltage of no greater than 4.0 VDC. The RADVR output is controlled by the state of the RA bit, except in pulse dial mode. When RA is a 1, the RADVR output is active which applies current to the relay coil. In a typical application, RADVR is connected to the normally open Off-Hook relay. In this case, RADVR active closes the Off-Hook relay to connect the modem to the telephone line. RBDVR OD Relay B Driver. RBDVR is an open drain output which can directly drive a relay with greater than 360 Q coil resistance and having a 'must operate' voltage of no greater than 4.0 VDC. RBDVR output is controlled by the state of the RB bit. When RB is a 1, the RBDVR output is active which applies current to the relay coil. In a typical application, RBDVR is connected to the normally closed Talk/Data relay. In this case, RBDVR active opens the relay to disconnect the handset from the telephone line. RING IA Ring Frequency. A low-going edge on the RING input initiates a ring frequency measurement. A valid ring detection is indicated by the RI bit.
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2.0 Hardware Interface
RC96V24DP
Single Device Data/Modem Data Pump
Table 2-2. Hardware Interface Signal Definitions (Continued) Label I/O Type
SPEAKER INTERFACE SPKR O(DF) Speaker Analog Output. The SPKR output reflects the received analog input signal. The SPKR on/off and three levels of attenuation are controlled by interface memory bits. When the speaker is turned off, the SPKR output is clamped to the voltage at the VC pin. The SPKR output can drive an impedance as low as 300 ohms. In a typical application, the SPKR output is an input to an external LM386 audio power amplifier. SLEEP MODE SIGNALS SLEEP SLEEP1 OA IA Sleep Mode Output and Sleep Mode Input. SLEEP output high indicates the DSP is operating in its normal mode. SLEEP low indicates that the DSP is in the sleep mode. This signal must be connected to the SLEEP1 input to power down the IA in the sleep mode. SLEEP can also be used to control power to other devices (e.g., as a speaker enable). DIAGNOSTIC SIGNALS Four signals provide the timing and data necessary to create an oscilloscope quadrature eye pattern. The eye pattern is simply a display of the received baseband constellation. By observing this constellation, common line disturbances can usually be identified. EYEX, EYEY OB Eye Pattern Data X and Eye Pattern Data Y. The EYEX and EYEY outputs provide two serial bit streams containing data for display on the oscilloscope horizontal (X) axis and vertical (Y) axis, respectively. This serial digital data can be converted to analog form using two shift registers and two digital-to-analog converters (DACs). Eye Pattern Clock. EYECLK is a clock for use by the serial-to-parallel converters. The EYECLK output is a 7200/9600 Hz clock. Eye Pattern Sync. EYESYNC is a strobe for word synchronization. The falling edge of EYESYNC may be used to transfer the 8-bit word from the shift register to a holding register. Digital-to-analog conversion can then be performed for driving the X and Y inputs of an oscilloscope. MODEM INTERCONNECT RFILO AGCIN MODEO (DSP) MODEI (IA) TDACO (DSP), TDACI (IA) TSTBO (DSP), TSTBI (IA) TRSTO (DSP), TRSTI (IA) MI MI MI Transmitter DAC Signal. Transmitter serial digital DAC signal. Direct modem interconnect line. Transmitter Strobe. Transmitter 576 kHz digital timing reference. Direct modem interconnect line. Transmitter Reset. Transmitter 7200/9600 Hz digital timing reference. Direct modem interconnect line. MI MI MI Receive Filter Output. RFILO is the output of the internal receive analog filter which must be connected to AGCIN through a 0.1 F, 20%, DC decoupling capacitor. Receive AGC Gain Amplifier Input. See RFILO. Mode Control. Serial IA mode control bits. Direct modem interconnect line.
Signal/Definition
EYECLK (RRSTO)
OA
EYESYNC
OB
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D96V24DSA
RC96V24DP
Single Device Data/Modem Data Pump
Table 2-2. Hardware Interface Signal Definitions (Continued) Label I/O Type
MODEM INTERCONNECT (con't) RADCI (DSP), RADCO (IA) RAGCO (DSP), RAGCI (IA) RSRBO (DSP), RSRBI (IA) RRSTO (DSP), RRSTI (IA) MI MI MI MI
2.0 Hardware Interface
Signal/Definition
Receiver ADC Signal. Receiver serial digital ADC signal. Direct modem interconnect line. Receiver AGC Signal. Receiver serial digital AGC signal. Direct modem interconnect line. Receiver Strobe. Receiver 576 kHz digital timing reference. Direct modem interconnect line. Receiver Reset. Receiver 7200/9600 Hz digital timing reference. Direct modem interconnect line.
Table 2-3. Digital Interface Characteristics Parameter
Input High Voltage Type IA Type ID Input Low Voltage Input Low Current Output High Voltage Types OA and OB Type OD Output Low Voltage Types OA and OC Type OB Type OD Three-State Input Current (Off) Power Dissipation Operating Sleep Note: ITSI PD - - 300 15 450 22.5 VOL - - - - - - 0.4 0.4 0.75 10 A mW VIL IIL VOH 3.5 - - - - Vcc Vdc ILOAD = 1.6 mA ILOAD = 0.8 mA ILOAD = 15 mA VIN = 0.4 to Vcc -1
Symbol
VIH
Min.
Typ.
Max.
Units
Vdc
Test Conditions(1)
2.0 0.8 (Vcc) -0.3 -
- - - -
Vcc Vcc 0.8 -400 Vdc A Vdc ILOAD = -100 A ILOAD = 0 mA Vcc = 5.25V
-
(1) Test Conditions: Vcc = 5V 5%, TA = 0C to 70C (unless otherwise noted).
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2.0 Hardware Interface
RC96V24DP
Single Device Data/Modem Data Pump
Table 2-4. Analog Interface Characteristics Name
RXA TXA1, TXA2 SPKR
Type
I (DA) O (DD) O (DF)
Characteristic
1458 type op amp input 1458 type op amp output 1458 type op amp output
2-10
D96V24DSA
3.0 Software Interface
3.1 Interface Memory
The DSP communicates with the host by means of a dual-port, interface memory The interface memory in the DSP contains thirty-two 8-bit registers, labeled register 00 through 1F. Each register can be read from, or written into, by both the host and the DSP. The host communicates with the DSP interface memory via the microprocessor bus. The host can control modem operation by writing control bits to DSP interface memory and writing parameter values to DSP RAM through the interface memory. The host can monitor modem operation by reading status bits from DSP interface memory and reading parameter values from DSP RAM through interface memory.
3.2 Interface Memory Map
A memory map of DSP interface memory identifying the contents of the 32 addressable registers is shown in Table 3-1. These 8-bit registers may be read or written during any host read or write cycle. In order to operate on a single bit or group of bits in a register, the host must read a register then mask out unwanted data. When writing a single bit or group of bits in a register, the host must perform a read-modify-write operation. That is, the host must read the entire register, set or reset the necessary bits without altering the other register bits, then write the unaffected and modified bits back into the interface memory register.
3.3 Interface Memory Bit Functions
Table 3-2 summarizes the functions of the individual bits in the interface memory. Bits in the interface memory are referred to using the format Z:Q. The register number is denoted by Z (00 through iF) and the bit number is located by Q (0 through 7, where 0 = LSB).
D96V24DSA
3-1
3.0 Software Interface
3.3 Interface Memory Bit Functions
RC96V24DP
Single Device Data/Modem Data Pump
Table 3-1. Interface Memory Map Register Function Register Address (Hex)
1F Interrupt Handling 1E 1D 1C 1B RAM Access, Control and Status 1A 19 18 17 16 - - Control 12 Transmit Data Buffer 11 10 0F 0E 0D Status 0C 0B 0A 09 08 07 06 Control 05 04 03 02 01 Receive Data Buffer 00 Note: RECEIVE DATA BUFFER (RBUFFER) ` - ' in the BIT columns indicates reserved for modem use only. - EQRES NRZIE - - - SWRES HDLC - - - - SPLIT - - TXSQ - - - - CEQE EQFZ ARC - - RCEQ IFIX SDIS - - TXVOC AGCFZ GTE - - - CRFZ - - RXP EDET TONEA - NV25 ASYNC RDLE BRKS - TONEB - CC TPDM RDL EXOS - TONEC - DTMF - L2ACT PARSL - ATV25 - ORG DDIS - ATBELL - LL TRFZ L3ACT PEN DTDIG PNSUC - DATA - RB STB DTDET - - RTRN RA BEL103 CRCS SLEEP RTS ABORT WDSZ RLSD RTDET - FED BRKD PNDET - - - CONFIGURATION (CONF) - - - - TXP 15 14 13 - - - - TLVL - - YACC - - TDBIA XACC RDBIA - TDBIE - - - TDBE IOX RDBIE XCRD - XWT RDBF XCR
Bit 7
NSIA
6
NCIA
5
-
4
NSIE
3
NEWS
2
NCIE
1
-
0
NEWC
X RAM ADDRESS (XADD) - - YCRD YWT YCR
Y RAM ADDRESS (YADD) X RAM DATA MSB (XDAM) X RAM DATA LSB (XDAL) Y RAM DATA MSB (YDAM) Y RAM DATA LSB (YDAL) - - - - VOL - - - - TXCLK - -
TRANSMIT DATA BUFFER (TBUFFER) CTS PE S1DET DSR FE SCR1 RI OE U1DET SADET TM SYNCD SPEED - - FLAGS
3-2
D96V24DSA
RC96V24DP
Single Device Data/Modem Data Pump
3.0 Software Interface
3.3 Interface Memory Bit Functions
Table 3-2. Interface Memory Bit Functions Mnemonic
ABORT AGCFZ ARC ASYNC ATBELL ATV25 BEL1O3 BRKD BRKS CC CEQ CONF CRCS CRFZ CTS DATA DDIS DSR DTDET DTDIG DTMF EDET EQFZ EQRES EXOS FE FED
Memory Location
07:0 04:1 03:3 08:7 OB:3 OB:4 OB:0 OE:6 06:7 09:6 05:3 12:0-7 OA:0 04:0 OF:5 09:2 08:4 OF:4 OB:1 00:0-3 09:5 00:7 04:3 04:7 06:6 OE:4 OF:6
Name/Description
HDLC Abort. Controls sending of continuous mark in HDLC mode. AGC Freeze. inhibits updating of the receiver AGC. Automatic Rate Change Enable. Enables automatic on-line rate change sequence. Asynchronous/Synchronous. Selects asynchronous or synchronous data mode. Bell Answer Tone Detected. Reports detection status of 2225 Hz answer tone. V25 Answer Tone Detected. Reports detection status of 2100 Hz answer tone. Bell 103 Mark Frequency Detected. Reports detection status of 1270 Hz Bell 103 mark. Break Detected. Reports receipt status of continuous space. Break Sequence. Controls sending of continuous space in parallel asynchronous mode. Controlled Carrier. Selects controlled or constant carrier mode. Compromise Equalizer Enable. Enables the transmit passband digital compromise equalizer. Modem Configuration Select. Selects the modem operating mode. CRC Sending. Reports the sending status of the CRC (2 bytes) in HDLC mode. CarrIer Recovery Freeze. Disables update of the receiver's carrier recovery phase lock loop. Clear to Send. Reports that the training sequence has been completed (see TPDM). Data Mode. Selects idle or data mode. Descrambler Disable. Disables the receiver's descrambler circuit. Data Set Ready. Reports the data transfer state. DTMF Digit Detected. Reports that a valid DTFM digit has been detected. Detected DTMF Digit. Contains the hexadecimal code of the detected DTMF digit. DTMF Dial Select. Selects either DTMF or pulse dialing in the dial mode. Early DTMF Detect. Reports detection of the high group frequency of the DTMF tone pair. Equalizer Freeze. inhibits the update of the receiver's adaptive equalizer taps. Equalizer Reset. Resets the receiver adaptive equalizer taps to zero. Extended Overspeed. Selects extended overspeed mode in asynchronous mode. Framing Error. Reports framing error detection or detection of an ABORT sequence. Fast Energy Detected. Reports energy above the turn-on threshold is being detected.
D96V24DSA
3-3
3.0 Software Interface
3.3 Interface Memory Bit Functions
RC96V24DP
Single Device Data/Modem Data Pump
Table 3-2. Interface Memory Bit Functions (Continued) Mnemonic Memory Location
OF:0 03:1 03:6 04:2 1D:3 07:5 07:3 09:3 1F:6 1F:2 I F:0
Name/Description
Flag Sequence. Reports transmission status of the Flag sequence in HDLC mode, or transmission of a constant mark in parallel asynchronous mode. Guard Tone Enable. Enables transmission of the 1800 Hz guard tone (CCITT configuration only). High Level Data Link Control. Enables HDLC protocol support in parallel data mode. Eye Fix. Forces EYEX and EYEY serial data to be rotated equalizer output. I/O Register Select. Specifies that the X RAM ADDRESS (XADD) is an internal I/O register address. Loop 2 (Local Digital Loopback) Activate. Selects connection of the receiver's digital output Internally to the transmitter's digital input (locally activated digital loopback). Loop 3 (Local Analog Loopback) Activate. Selects connection of the transmitter's analog output Internally to the receiver's analog input (local analog Ioopback). Leased Line. Selects leased line data mode or handshake mode. NEWC Interrupt Active. Reports that the cause of an interrupt request was completion of a configuration change. (See NEWC and NCIE.) NEWC interrupt Enable. Enables the assertion of IRQ and the setting of the NCIA bit. New Configuration. Initiates a new configuration; cleared by the modem upon completion of configuration change. This bit can cause IRQ to be asserted. (See NCIE and NCIA.) New Status. Reports the detection of a change In selected status bits. This bit can cause IRQ to be asserted. (See NSIE and NSIA.) NEWS Interrupt Active. Reports that the cause of an interrupt request was a status bit change. (See NEWS and NSIE.) NEWS interrupt Enable. Enables the assertion of IRQ and the setting of the NSIA bit. (See NEWS.) Disable V.25 Answer Sequence (Data Modes), Disable Echo Suppressor Tone (Fax Modes). Disables the transmitting of the 2100 Hz CCI1T answer tone when a handshake sequence Is initiated In a data mode or disables sending of the echo suppressor tone in a fax mode. Overrun Error. Reports overrun status of the Receiver Data Buffer (RBUFFER). Originate. Selects originate or answer mode. Parity Error. Reports parity error status or bad CRC PN Success. Indicates that the receiver has detected the PN portion of the training sequence. Relay A Activate. Activates the RADRV output. Parity Select. Selects stuff, space, even, or odd parity in the asynchronous parallel data mode.
FLAGS GTE HDLC IFIX IOX L2ACT L3ACT LL NCIA NCIE NEWC
NEWS NSIA NSIE
1F:3 1F:7 1F:4
NV25
09:7
OE ORG PE PNSUC RA PARSL
OE:3 09:4 OE:5 OB:2 07:1 06:4.5
3-4
D96V24DSA
RC96V24DP
Single Device Data/Modem Data Pump
Table 3-2. Interface Memory Bit Functions (Continued) Mnemonic
RB RBUFFER RDBF RDBIA RDBIE RDL RDLE PEN RCEQ RI RTDET RTRN RTS RLSD RXP S1DET SADET SCR1 SDIS SLEEP SPEED SPLIT STB SWRES
3.0 Software Interface
3.3 Interface Memory Bit Functions
Memory Location
07:2 00:0-7 1E:0 1E:6 I E:2 07:6 07:7 06:3 05:2 0F:3 0E:7 08:1 08:0 0F:7 01:0 00:5 00:2 00:4 03:2 09:0 0E:0-2 03:5 06:2 04:6
Name/Description
Relay B Activate. Activates the RBDVR output. Receive Data Buffer. Contains the received byte of data. Receiver Data Buffer Full. Reports the status (full or not full) of the Receiver Data Buffer (RBUFFER). (See RDBIE and RDBIA.) Receiver Data Buffer interrupt Active. Reports that the cause of an interrupt request Is the Receiver Data Buffer (RBUFFER) full. (See RDBF and RDBIE.) Receiver Data Buffer interrupt Enable. Enables the assertion of IRQ and the setting of the RDBIA bit when RBUFFER is full. (See RDBF and RDBIA.) Remote Digital Loopback Request. initiates a request for the remote modem to go into digital loop-back. Remote Digital Loopback Response Enable. Enables the modem to respond to the remote modem's digital loopback request. Parity Enable. Enables generation/checking of parity in asynchronous parallel data mode. Receiver Compromise Equalizer Enable. Controls insertion of the receive passband digital compromise equalizer into the receive path. Ring Indicator. Reports detection status of a valid ringing signal. Retrain Detected. Reports detection status of a retrain request sequence. Retrain. Controls sending of the retrain request or automatic rate change to the remote modem. Request to Send. Requests the transmitter to send data. Received Line Signal Detector. Reports detection status of the carrier and the receipt of valid data. Received Parity bit. This bit is the received parity bit (or ninth data bit). S1 Sequence Detected. Reports detection status of the S1 sequence. Scrambled Alternating Ones Sequence Detected. Reports detection status of the Scrambled Alternating Ones sequence. Scrambled Ones Sequence Detected. Reports detection status of Scrambled Ones sequence. Scrambler Disable. Disables the transmitter scrambler. Sleep Mode. Controls entry Into the SLEEP mode. The modem requires a pulse on the RESET pin to return to normal operation. Speed Indication. Reports the data rate at the completion of a connection. Extended Overspeed TX/RX Split. Limits transmit data to the basic overspeed rate. Stop Bit Number. Selects the number of stop bits in asynchronous mode. Software Reset. Causes the modem to reinitialize to Its power turn-on state.
D96V24DSA
3-5
3.0 Software Interface
3.3 Interface Memory Bit Functions
RC96V24DP
Single Device Data/Modem Data Pump
Table 3-2. Interface Memory Bit Functions (Continued) Mnemonic
TBUFFER TDBE TDBIA TDBIE
Memory Location
10:0-7 1E:3 1E:7 1E:5
Name/Description
Transmitter Data Buffer. Contains the byte to be transmitted in the parallel mode. Transmitter Data Buffer Empty. Reports the status (empty or not empty) of the Transmit Data Buffer (TBUFFER). (See TDBIE and TDBIA.) Transmitter Data Buffer Interrupt Active. Reports that the cause of an interrupt request Is the Transmit Data Buffer (TBUFFER) empty. (See TDBE and TDBIE.) Transmitter Data Buffer interrupt Enable. Enables assertion of IRQ and the setting of the TDBIA bit when the TBUFFER is empty. (See TDBE and TDBIA.) Transmit Level Attenuation Select. Selects the transmitter analog output level attenuation In 1 dB steps. The host can fine tune the transmit level to a value lying within a 1 dB step In DSP RAM. Test Mode. Reports active status of the selected test mode. Tone Filter A Energy Detected. Reports status of energy above the threshold detection by the Call Progress Monitor filter in the Dial Configuration or 1300 Hz FSK tone energy detection by the Tone A bandpass filter In the Tone Detector configuration. Tone Filter B Energy Detected. Reports status of 390 Hz FSK tone energy detection by the Tone B bandpass filter in the Tone Detector configuration. Tone Filter C Energy Detected. Reports status of 1650 Hz or 980 Hz (selected by the ORG bit) FSK tone energy detection by the Tone C bandpass filter in the Tone Detector configuration. Transmitter Parallel Data Mode. Selects transmitter parallel or serial mode. Timing Recovery Freeze. Inhibits the update of the receiver's timing recovery algorithm. Transmit Clock Select. Selects the transmitter data clock (internal, disable, slave, or external). Transmit Parity Bit (or 9th Data Bit). This bit Is the stuffed parity bit (or ninth data bit) for transmission. Transmitter Squelch. Disables transmission of energy. Transmit Voice. Enables the sending of voice samples. Unscrambled Ones Detected. Reports detection status of the Unscrambled Ones sequence. Data Word Size. Selects the number of data bits per character in asynchronous mode (5, 6, 7. or 8). Volume Control. Two-bit encoded speaker volume selects volume off or one of three volume on levels. X RAM Access Enable. Controls DSP access of the X RAM associated with the address in XADD and the XCR bit. XWT determines it a read or write is performed. X RAM Address. Contains the X RAM address used to access the DSP's X Data RAM or X Coefficient RAM (selected by XCR) via the X RAM Data LSB and MSB registers.
TLVL TM TONEA
13:4-7 0F:2 0B:7
TONEB
OB:6
TONEC TPDM TRFZ TXCLK TXP TXSQ TXVOC U1DET WDSZ VOL XACC XADD
05:5 08:6 08:3 13:0,1 11:0 05:4 05:1 OD:3 06:0,1 13:2-3 1D:7 1C:0-7
3-6
D96V24DSA
RC96V24DP
Single Device Data/Modem Data Pump
Table 3-2. Interface Memory Bit Functions (Continued) Mnemonic Memory Location
1D:0 1D:2 18:0-7 19:0-7 1D:1 1B:7 1A0-7 15:0 15:2 16:0-7 17:0-7 1B:1
3.0 Software Interface
3.4 DSP RAM Access
Name/Description
X Coefficient RAM Select. Controls XADD access to the DSP's X Coefficient RAM or the X Data RAM. X RAM Continuous Read. Enables read of X RAM every sample from the location addressed by XADD independent of the XACC and XWT bits. X RAM Data LSB. The least significant byte of the 16-bit X RAM data word used in reading or writing X RAM locations in the DSR X RAM Data MSB. The most significant byte of the 16-bit X RAM data word used In reading or writing X RAM locations in the DSR X RAM Write. Controls the reading of data from, or the writing of data to, the X RAM Data registers (18 and 19) using the X RAM location addressed by XADD and XCR. Y RAM Access Enable. Controls DSP access of the Y RAM associated with the address In YADD and the YCR bit. YWT determines if a read or write is performed. Y RAM Address. Contains the Y RAM address used to access the DSP's V Data RAM or V Coefficient RAM (selected by YCR) via the Y RAM Data LSB and MSB registers. Y Coefficient RAM Select. Controls YADD access to the DSP's Y Coefficient RAM or the Y Data RAM. Y RAM Continuous Read. Enables read of Y RAM every sample from the location addressed by YADD Independent of the YACC and YWT bits. Y RAM Data LSB. The least significant byte of the 16-bit Y RAM data word used in reading or writing Y RAM locations in the DSP Y RAM Data MSB. The most significant byte of the 16-bit Y RAM data word used in reading or writing Y RAM locations in the DSP. Y RAM Write. Controls the reading of data from, or the writing of data to. the Y RAM Data registers (16 and 17) using the Y RAM location addressed by YADD and YCR.
XCR XCRD XDAL XDAM XWT YACC YADD YCR YCRD YDAL YDAM YWT
3.4 DSP RAM Access
The DSP contains four sections of 16-bit wide random access memory (RAM). Because the DSP is optimized for performing complex arithmetic, the RAM is organized into real (X RAM) and imaginary (Y RAM) sections, as well as data and coefficient sections. The host processor can access (read or write) the X RAM only, the Y RAM only, or both the X RAM and the Y RAM simultaneously in either the data or coefficient section.
D96V24DSA
3-7
3.0 Software Interface
3.5 Interface Memory Access to DSP RAM
RC96V24DP
Single Device Data/Modem Data Pump
3.5 Interface Memory Access to DSP RAM
The DSP Interface memory acts as an intermediary during host to DSP RAM or DSP RAM to host data exchanges. The addresses stored in modem Interface memory RAM Address registers (i. e., XADD and YADD) by the host, in conjunction with the data or coefficient RAM bits (i. e., XCR and YCR) determine the DSP RAM addresses for data access.
3.6 Host Programmable Data
The parameters available In DSP RAM are listed in Table 3-3 along with the X RAM or Y RAM address and corresponding XCR or YCR bit value. The scaling for the host programmable data is described in the Modem Designer's Guide.
Table 3-3. DSP RAM Parameters No. XCR/YCR(1)
1 1 1 1 1 1 1 2 1 1 3 4 5 6 7 8 9 10 0 0 0 0 0 0 0 0 - - 49 - 3F 71 7C 72 7D 7E 10 1E - 49 - - - - - - Last Coefficient, Imag. (17) (Data) Last Coefficient, Imag. (31) (Fax) Rotated Error, Real Rotated Error, Imaginary Max AGC Gain Word Pulse Dial Interdigit Time Tone Dial Interdigit Time Pulse Dial Relay Make Time Pulse Dial Relay Break Time DTMF Duration - 10 1E - - 0-1E 0 Last Coefficient, Real (17) (Data) Last Coefficient, Real (31) (Fax) Adaptive Equalizer Coefficients, Imag. First Coefficient, Imag. (1) (Data/Fax)
X RAM Addr
0-1E 0
Y RAM Addr
Parameter
Adaptive Equalizer Coefficients, Real
-
First coefficient, Real (1) (Data/Fax)
3-8
D96V24DSA
RC96V24DP
Single Device Data/Modem Data Pump
Table 3-3. DSP RAM Parameters (Continued) No.
11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
3.0 Software Interface
3.6 Host Programmable Data
XCR/YCR(1)
0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
X RAM Addr
6C 6D 6E 6F 73 74 5E - - 59 - 3C - 3F 3E 2E 2D 2F 30 31 36 37 38
Y RAM Addr
- - - - - - - 5E 3D - 59 - 3C - - - - - - - - - -
Parameter
Tone 1 Angle Increment Per Sample (TXDPHI1) Tone 2 Angle Increment Per Sample (TXDPHI2) Tone 1 Amplitude (TXAMP1) Tone 2 Amplitude (TXAMP2) Max Samples Per Ring Frequency Period (RDMAXP) Min Samples Per Ring Frequency Period (RDMINP) Real Part of Error Imaginary Part of Error Rotation Angle for Carrier Recovery Rotated Equalizer Output, Real Rotated Equalizer Output, Imaginary Lower Part of Phase Error Upper Part of Phase Error Upper Part of AGC Gain Word Lower Part of AGC Gain Word Average Power Phase Error Tone Power (TONEA) Tone Power (ATBELL, BEL103, or TONEB) Tone Power (TONEC, ATV25) Tone Detect Threshold for TONEA (THDA) Tone Detect Threshold for ATBELL, BEL103, or TONEB (THDB) Tone Detect Threshold for TONEC or ATV25 (THDC)
D96V24DSA
3-9
3.0 Software Interface
3.7 Modem Interface Circuit
RC96V24DP
Single Device Data/Modem Data Pump
Table 3-3. DSP RAM Parameters (Continued) No. XCR/YCR(1)
1 1 1 1 1 34 1 1 1 1 1 35 36 37 38 39 0 1 1 0 1 - - - - - 32 79 - 70 52 71-75 76-7A 7B-7F 62-66 67-6B - - 21 - -
X RAM Addr
- - - - -
Y RAM Addr
6C 6D 6E 6F 70 Biquad 1 Coefficient 0 Biquad 1 Coefficient 1 Biquad 1 Coefficient 2 Biquad 1 Coefficient 1 Biquad 1 Coefficient 2
Parameter
Biquad 2 Coefficients 0 - 2 Biquad 3 Coefficients 0 - 2 Biquad 4 Coefficients 0 - 2 Biquad 5 Coefficients 0 - 2 Biquad 6 Coefficients 0 - 2 Turn-on Threshold Turn-off Threshold RLSD Turn-off Time Transmit Level Output Attenuation Eye Quality Monitor (EQM)
Note: (1)XCR if an XRAM address is listed; YCR if a YRAM address is listed.
3.7 Modem Interface Circuit
The recommended modem Interface circuit is shown in Figure 3-1.
3-10
D96V24DSA
RC96V24DP
Single Device Data/Modem Data Pump
3.0 Software Interface
3.7 Modem Interface Circuit
Figure 3-1. Typical Modem Interface Circuit
VCC VCC C14 .1 C15 .1 C21 .1
VCC C9 12 10% 20V
L1 47 C8 .1 U7
13 4 27 46 9 8 7 10 62 61 60 59 58 57 56 55 63 64 66 65 67 68 1 2 3 16 18 19 28 29 15 17 54 40 VCC TEST* RRSTO RRSTI EYESYNC EYEX EYEY RESET* D0 D1 D2 D3 D4 D5 D6 D7 IRQ* WRITE* READ* CS* RS4 RS3 RS2 RS1 RS0 XTCLK TXD TDCLK RDCLK* RXD GP16 DGND1 DGND2 AGND VAA XTLO XTLI TDACO TDACI MODEO MODEI TRSTO TRSTI RSTBO RSTBI TSTBO TSTBI RADCO RADCI RAGCO RAGCI RBVDR* RADVR RXA TXA1 TXA2 VC RING* AGCIN RFILO SLEEP* SLEEPI* SPKR NC NC NC NC GP18 52 12 11 22 48 25 51 20 49 26 45 21 50 47 23 24 43 39 41 32 31 30 35 6 34 33 5 42 53 36 37 38 44 14
R13 1 8 0k R E S ET* C8 .1
EYECLK EYESYNC E Y EX EYEY D0 D1 D2 D3 D4 D5 D6 D7 IRQ* WRITE* READ* CS* RS4 RS3 RS2 RS1 RS0 XTCLK TXD T D C LK RDCLK* RXD R E S ET*
R12 100
DECOUPLING CAPS C 1 7 5 6 PF 5% 1 3 2 Y1
1 6 .000312MHZ
C7 5 6 PF 5%
VCC
RADVR* RXA TXA1 TXA2 RING*
TO DAA INTERFACE
C12 .1
6 1
C5 2200 pF
C18 .1 uF C10 2 7 3 C11 .1
U6 LM386
+ -
C16 220 16V
LS1
5 C13 10 16V 161201
C18 1 0 0 0 pF
RC96V24
Figure 3-2. Typical DAA Interface Circuit
4 8
.1
RADVR* RXA C20 .1 R6 536 1% D4 1 N 749A VCC D5 1 N 749A TXA1 TXA2 RING* C4 .022uF T1 LINE TTC143 VCC 4 2 3
K1 1 R 1 0 18
RV1 V150LA2 RELAY R1 C3 .47 10% 250V D3 1 N 4148 R2 7.5K 1W D1 1 N 970B 18 1W
TOP
8 1 2 3 4 5 6 7
J4 T E L CO4/6
R3 100K 5 4 6
U1 2 3 1 4 N 35
C2 .001 10% 1KV
C1 .001 10% 1KV
8 1 2 3 4 5 6 7
J3 T E L CO4/6
TOP
D2 1 N 970B
D96V24DSA
3-11
3.0 Software Interface
3.7 Modem Interface Circuit
RC96V24DP
Single Device Data/Modem Data Pump
3-12
D96V24DSA
Because Communication MattersTM
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(972-9) 9524 000 (972-9) 9573 732
(55-11) 3874 8978 (55-11) 3874 8883
Document Number:
D96V24DSA

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